In association with increase in an operating speed of circuits, noise caused due to inductance of inner lead or bonding wires or the like of the package is creating a problem. A reverse electromotive force that is a product of a time-related change rate of a current and self inductance is generated. The reverse electromotive force creates noise in the power supply potential or a ground potential. FIG. 15 is a circuit diagram showing configuration of an output buffer circuit that reduces the generation of noise as described above in a conventional type of semiconductor integrated circuit. In FIG. 15, designated at the reference numeral 1 is an input terminal into which an output signal IN1 from an internal circuit is inputted. The numeral 2' is an output terminal, 5 is a power supply potential, 6 is a ground potential, P1 to P4 are P-channel type metal oxide semiconductor transistor (described as PMOS transistor hereinafter), N1 to N4 are N-channel type metal oxide semiconductor transistor (described as NMOS transistor hereinafter), 9a is a pre-driver circuit and 10a is a main driver circuit.
Source electrode of the PMOS transistor P1 of the pre-driver circuit 9a is connected to the power supply potential 5, gate electrode is connected to the input terminal 1 and drain electrode is connected to a node np0. Source electrode of the NMOS transistor N2 is connected to the ground potential 6, gate electrode connected to the input terminal 1 and drain electrode is connected to the source electrode of NMOS transistor N1. The gate electrode of NMOS transistor N1 is connected to the input terminal 1 and drain electrode is connected to the node np0. This forms an inverter for driving a gate electrode of a PMOS transistor P4 of the main driver circuit 10a. Source electrode of the PMOS transistor P2 is connected to the power supply potential 5, gate electrode is connected to the input terminal 1 and drain electrode is connected to a source electrode of PMOS transistor P3. Gate electrode of PMOS transistor P3 is connected to the input terminal 1 and drain electrode is connected to the node nn0. Source electrode of NMOS transistor N2 is connected to the ground potential 6, a gate electrode is connected to the input terminal 1 and drain electrode is connected to the node nn0. This forms an inverter for driving a gate electrode of a NMOS transistor N4 of the main driver circuit 10a.
Source electrode of the PMOS transistor P4 of the main driver circuit 10a is connected to the power supply potential 5, gate electrode is connected to the node np0 and drain electrode is connected to the output terminal 2'. Source electrode of NMOS transistor N4 is connected to the ground potential 6, gate electrode is connected to the node nn0 and drain electrode is connected to the output terminal 2'.
In the conventional type of circuit as shown in FIG. 15, MOS transistors N1 and P3 are provided in an ordinary output buffer circuit to suppress a through rate (time differential of an output voltage) of an output signal to a certain value or less for reducing noise. Namely, between the main driver circuit 10a provided in a final output state so that the DC characteristics of an output buffer circuit is not affected and the pre-driver circuit 9a provided before the main driver circuit 10a, a gradient is applied to a signal by making use of ON resistance of the MOS transistor provided for noise reduction to achieve a reduction in the noise.
More specifically, when the potential at output terminal 2' shifts from "L" or "H", shift of a voltage level at the node np0 is, as shown in FIG. 17A, expressed by a curve with the gradient from "H" to "L" becoming dull due to ON resistance of the NMOS transistor N1 connected in series thereto for noise reduction. On the other hand, a shift of a voltage level to "L" level at the node nn0 is quickly executed by the NMOS transistor N3. For this reason, potential at the output voltage 2' quickly shifts from "L" to "H".
When the potential at output terminal 2' shifts from "H" to "L", shift of a voltage level at the node np0 is, as shown in FIG. 17B, executed quickly by the PMOS transistor P1 from "L" to "H". On the other hand, shift of a voltage level at the node nn0 is expressed with a curve with the gradient from "L" to "H" becoming gentler due to ON resistance of the PMOS transistor P3 connected in series for noise reduction. For this reason, potential at the output terminal 2' shifts gradually from "H" to "L". In either case of output voltage shifting from "L" to "H" or from "H" to "L", by making smaller a time change ratio of di/dt of a charge or discharge current to or from a loaded capacity with the MOS transistors N1 and P3 each for noise reduction for in turn making smaller a reverse electromotive force decided by a product of self inductance in a bonding wire, package inner lead or the like and di/dt, it is possible to reduce noise in power supply potential or ground potential generated by the reverse electromotive force.
FIG. 16 is a circuit diagram showing other configuration of an output buffer circuit designed to reduce generation of noise in the conventional type of semiconductor integrated circuit. In FIG. 16, designated at the reference 1 is an input terminal into which an output signal IN1 from an internal circuit is inputted. 2' is an output terminal, 3 is an input/output control terminal for receiving an input/output control signal IN2 from the internal circuit, 5 is a power supply potential, 6 is a ground potential, P4 to P14 are PMOS transistors, N4 to N14 are NMOS transistors, np1 to np3 and nn1 to nn3 are nodes, 8a is an output state control circuit, 9b is a pre-driver circuit and 10a is a main driver circuit.
The output state control circuit 8a comprises an inverter in turn comprising a PMOS transistor P5 having a source electrode connected to the power supply potential 5 and a gate electrode connected to the input/output control terminal 3 and a NMOS transistor N5 having source electrode connected to the ground potential 6 and a gate electrode connected to the input/output control terminal 3. There is a two-input NAND gate in turn comprising a PMOS transistor P6 having a source electrode connected to the power supply point 5, gate electrode connected to the input terminal 1 and drain electrode connected to the node np1; a PMOS transistor P7 having a source electrode connected to the power supply potential 5, gate electrode connected to an output terminal of said inverter and drain electrode connected to the node np1; a NMOS transistor N7 having a source electrode connected to the ground potential 6 and a gate electrode connected to an output terminal of the inverter; and a NMOS transistor N6 having a source electrode connected to a drain electrode of the NMOS transistor N7, gate electrode connected to the input terminal 1 and drain electrode connected to the node np1. There is a two-input NOR gate in turn comprising PMOS transistor P8 having a source electrode connected to the power potential 5 and a gate electrode connected to the input/output control terminal 3; a PMOS transistor P9 having a source electrode connected to a drain electrode of the PMOS transistor 8, gate electrode connected to the input terminal 1 and drain electrode connected to the node nn1; a NMOS transistor N8 having a source electrode connected to the ground potential 6, gate electrode connected to the input terminal 1 and drain electrode connected to the node nn1, and a NMOS transistor N9 having a source electrode connected to the ground potential 6, gate electrode connected to the input/output control terminal 3 and drain electrode connected to the node nn1.
The pre-driver circuit 9b shown in FIG. 16 shows configuration in which, in comparison to the pre-driver circuit 9a of FIG. 15, an inverter comprising PMOS transistor P10 and NMOS transistor N10 is inserted into a signal flow path between the nodes np1 and np2 and an inverter comprising PMOS transistor P11 and NMOS transistor N11 is inserted into a signal flow path between the nodes nn1 and nn2.
The main driver circuit. 10a comprises a PMOS transistor P4 having a source electrode connected to the power supply potential 5, gate electrode connected to the node np3 and drain electrode connected to the output terminal 2'; and a NMOS transistor N4 having a source electrode connected to the ground potential 6, gate electrode connected to the node nn3 and drain electrode connected to the output terminal 2'.
In the conventional type of circuit shown in FIG. 16, if the input/output control signal IN2 is at "H" level, the contact np1 of the output state control circuit 8a is "H" level (power supply potential) and the node nn1 is at "L" level (ground potential) regardless of whether the output signal IN1 is at "L" level or at "H" level. Then both the PMOS transistor P4 and NMOS transistor N4 in the main driver circuit 10a are turned OFF and the main driver circuit 10a is set in a high impedance state against the output terminal 2'.
On the other hand, if the input/output control signal IN2 is at "L" level, when the ouput signal IN1 is at "H" level, output from the output state control circuit 8a is set in "L" level at both the nodes np1 and nn1. Then, via the pre-driver circuit 9a in the latter stage, "L" level is given to the gate electrodes of PMOS transistor P4 and NMOS transistor N4 in the main driver circuit 10a in the final stage with the PMOS transistor P4 turned ON and further the NMOS transistor N4 turned OFF, and "H" level is outputted to the output terminal 2'.
If the output control signal is at "L" level, when the output signal is at "L" level, output from the output state control circuit 8a is set in "H" level at both the nodes np1, nn1. And, via pre-driver circuit 9b in the latter stage, "H" level is given to the gate electrodes of both PMOS transistor P4 and NMOS transistor N4, the PMOS transistor P4 is turned OFF and NMOS transistor N4 is turned ON, and "L" level outputted to the output terminal 2'.
In the example shown in Fig. 16, like in the example shown in FIG. 15, a certain gradient is applied to a signal in a pre-driver circuit to make a voltage shift time at the output terminal gentler in order to reduce the noise.
As described above, in the conventional type of circuit, by inserting a MOS transistors for noise reduction into one of inverters provided in the pre-driver circuit, a certain gradient is given to a signal by using the ON resistance, and as a result a voltage shift time at the output terminal can be made gentler. Because of this feature, noise caused by the excessive current which is generated due to a capacitive load loaded to the output terminal can be reduced. However, in the conventional configuration, it is difficult to obtain a desired shift time. To obtain a longer shift time, a number of stage of MOS transistors connected in series for noise reduction (a number of serially connected stages) need to be increased, but then propagation delay time of a signal becomes disadvantageously longer.
Generally in a semiconductor integrated circuit based on the conventional technology, a signal propagation delay time or a noise allowance value for each signal vary from device to device, and there is a need to develop a semiconductor integrated circuit in which the values can be set as desired.